1. Field of the Invention
The present invention relates to an electronic apparatus applying a unified non-volatile memory and a unified non-volatile memory controlling method, and particularly relates to an electronic apparatus applying a unified non-volatile memory and a unified non-volatile memory controlling method, which can adjust a refresh rate for a ram of the unified non-volatile memory based on a number of access times.
2. Description of the Prior Art
A conventional electronic apparatus always comprises at least one volatile memory and a non-volatile memory for different applications. Many conventional techniques have disclosed such architecture.
FIG. 1 is a block diagram illustrating a conventional electronic apparatus. As show in FIG. 1, the electronic apparatus 100 comprises a volatile memory 101, a non-volatile memory 103, and a control unit 105. The volatile memory 101, for example, a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), can keep data when it is provided power but loses data while power is removed. On the contrary, the non-volatile memory 103, for example, a ROM (read only memory) or a flash memory, can keep data even it is not provided power.
Since the non-volatile memory 103 has lower cost, the non-volatile memory 103 is applied as a main storage to store data necessary for the electronic apparatus, for example, the code for the control unit 105. However, the access speed of the non-volatile memory 103 is low. Therefore, the volatile memory 101 is always applied to temporarily store data to speed up the access operation for the whole electronic apparatus 100, since the volatile memory 101 has high access speed.
However, the volatile memory 101 has high cost. Also, some volatile memories such as DRAMs need to be frequently refreshed thus the power consumption is high, such that the battery life for the electronic apparatus is short.
Therefore, an electronic apparatus which needs long battery life is not suitable to apply the architecture depicted in FIG. 1.
Further, many methods have been applied to extend the endurance of memories, for example, ECC error correcting or detecting the access times of each bit. However, such methods always need a complex algorithm.